1. Technical Field
The present invention relates to a device having a shared memory, more specifically to a digital processing device having a memory shared by a plurality of processor and a code data transmitting method.
2. Description of the Related Art
A typical digital processing device is realized to include a plurality of processors. For example, a mobile communication terminal having a camera function includes a main processor, controlling a general operation of the mobile communication terminal, and an application processor, for performing a predetermined function (e.g. the camera function). The main processor can control to start/end an operation of the application processor. It is obvious that the quantity and type of the application processor mounted on the digital processing device are varied depending on the function of the digital processing device.
FIG. 1 is a block diagram illustrating the structure that a main processor and an application processor share a application memory, coupled to the application memory, with each other in accordance with the conventional art. The below description assumes that the application processor is a multimedia processor (i.e. a processor for controlling an image sensor 160 and performing the processing of multimedia data inputted from the image sensor 160).
Referring to FIG. 1, a main processor 110 includes a plurality of processors (e.g. a first memory controller 112 and a second memory controller 114. The main processor 110 accesses an application processor 120 through an MP (main processor)-AP (application processor) bus according to an operation of the first memory controller 112. The main processor 110, accessing the application processor 120, writes data in an application memory 140 or reads data stored in the application memory 140, by a path control of the application processor 120.
Also, the main processor 110 writes data or reads written data by accessing a main memory 130, which is directly coupled to the main processor 110 through an MP-MM (main memory) bus according to an operation of the second memory controller 114. Here, the main memory 130 is assumed to be a nonvolatile memory.
The application processor 120 includes an interface 121, a controller 123, an image scaler 125, a multimedia processing unit 127 and a memory control unit 129.
The application processor 120 is coupled to the application memory 140 having one port through an AP-AM (application memory) bus. The application processor 120 can be coupled to a display unit 150 for displaying the processed multimedia data.
The interface 121 transmits and receives data between the application processor 120 and the main processor 110. If a control signal is received from the main processor 10 through the interface 121, the application processor 120 performs a corresponding processing operation. For example, if a preview command (e.g. a command instructing to display a preview screen on the display unit 150 before capturing an external image) is received from the main processor 110, the application processor 120 processes the received preview command such that a real-time image corresponding to a real-time image signal inputted from a image sensor 160 can be displayed through the display unit 150.
The controller 123 controls an operation of the application processor 120 by using an installed program for operating the application processor 120 according to the control signal received from the main processor 110. The controller 123 can be a microcontroller unit (MCU), for example. For example, the controller 123 can control an overall operation of the application processor 120, read data necessary when executing the program from the application memory 140 and store the programming result in the application memory 140. The data necessary when executing the program, which the main processor 110 reads from the main memory 130 and provides to the application processor 120 through the MP-AP bus, can be written in the application memory 140 by the main processor 110 according to the path control of the application processor 120 or can be written in the application memory 140 by the application processor 120. The controller 123 can access the application memory 140 through a system bus 170 and the memory control unit 129 in order to read the data when executing the program.
According to the control of the controller 123, the image scaler 125 processes an image signal inputted from the image sensor 160 (or data processed by an image signal processor (ISP)) and converts the processed image signal to predetermined data. The image scaler 125 performs size control and color change of an image and soft image generation by filtering, for example. The data processed by the image scaler 125 is stored in the application memory 140 through the AP-AM bus according to path setting by the memory control unit 129.
The multimedia processing unit 127 reads image data stored in the application memory 140 to compress the image data in a predetermined format (e.g. MPEG-4 and JPEG) or give a necessary effect. Also, the multimedia processing unit 127 reads and decodes the compressed file, which is received from the main processor 110 and stored in the application memory 140, and then displays the decoded file on the display unit 150.
If internal elements of the application processor 120 require to access the application memory 140 together, the memory control unit 129 determines the priority order of the internal elements in order to allow any one of the internal elements to access the application memory 140. Also, if the main processor 110 and the application processor 120 require to access the application memory 140 together, the memory control unit 129 can control any one processor to access the application memory 140 by referring to predetermined priority order.
As such, the conventional memory has the structure that a plurality of processors or elements access one memory through one bus. Accordingly, the main processor has many time limits to use the memory of a particular application processor.
For example, in case that the main processor 110 transmits a boot program code (i.e. code data necessary for the application processor 120 to be booted), stored in the man memory 130, to the application memory 140, the main processor 110 should read the boot program code, which is stored in the main memory 130 through the MP-MM bus, and then transmit the boot program code to the application processor 120 through the MP-AP bus. Then, the application processor 120 writes the boot program code) transmitted through the main processor 10, in the application memory 140 connected to the application processor 120 through the AP-AM bus.
Accordingly, in accordance with the conventional memory sharing structure, the larger data, transferred between processors, causes many limits to use the application memory 140 connected to the application processor. This is because each internal element, included in the application processor 120, must use the AP-AM bus, connected to the application memory 140, in order to perform a processing operation.
As described above, the conventional memory sharing structure has many time delays to process high-functional and high-quality image. Also, this results in the decrease of the processing efficient of the application processor.